Programmable logic devices (PLDS) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLS, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDS), or in any other type of memory cell. Programmable devices can also be implemented in other ways, e.g., using fuse or antifuse technology. However, for the purposes of the present specification, the term “PLD” is used to describe a re-programmable programmable logic device, e.g., an FPGA, CPLD, or other re-programmable device.
As PLD designs increase in complexity, they reach a point at which the designer cannot deal with the entire design at the gate level. Where once a typical PLD design comprised perhaps 5,000 gates, PLD designs with over 100,000 gates are now common. To deal with this complexity, circuits are typically partitioned into smaller circuits that are more easily handled. Often, these smaller circuits are divided into yet smaller circuits, imposing on the design a multi-level hierarchy of logical blocks.
Libraries of pre-developed blocks of logic (“cores” or “macros”) have been developed that can be included in a PLD design. Such cores can include, for example, adders, multipliers, filters, and other arithmetic and DSP functions from which complex designs can be readily constructed. The use of pre-developed cores permits faster design cycles, by eliminating the redesign of duplicated circuits. Further, the library cores provided by PLD vendors or associated core providers are typically well tested, thereby making it easier to develop a reliable complex design.
Techniques such as the provision of cores are helpful in resolving some of the design issues facing system designers, such as time-to-market and product reliability. However, additional issues remain.
One issue that can sometimes be a design challenge is the provision for alterations in a design at a future time. For example, design changes can be necessitated by errors in the original design that are discovered after a product is placed into production. As another example, desired improvements to the product can be made over time, e.g., in future revisions of the product. PLDs are well suited for use in such systems due to the re-programmable nature of the PLDs. When a design change is desired, a designer can alter the original design, generate new configuration data for the altered design, and provide the new configuration data to the PLD, often while the PLD is still present in the system. Such changes can even be made remotely in some cases, e.g., over the Internet. To allow for such design changes, it is not uncommon for a designer to leave some “extra room” (i.e., unused programmable resources) in a PLD design.
However, when additional logic is added to an existing design, sometimes the new design does not function properly due to the additional noise generated by the additional logic. Time-consuming debug and redesign can be required to produce a properly functioning new design. Even when the new design appears to function properly, a designer typically does not assume that the original functionality is unaffected by the additional noise. Therefore, the designer typically re-qualifies the design by performing a series of tests designed to verify not only the new functionality, but also the original functionality that should not have been affected by the additional logic.
Therefore, it is desirable to provide methods that enable the revision of an existing PLD design and/or the addition of new logic to an existing PLD design without introducing additional noise that can adversely affect the existing design.